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https://community.intel.com/t5/Application-Acceleration-With/Agilex-5-Precision-DSP-block-simulations/m-p/1710248

Re: Agilex 5 Precision DSP block simulations

Hi, Thank you for looking into this further. I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared



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Re: Agilex 5 Precision DSP block simulations

https://community.intel.com/t5/Application-Acceleration-With/Agilex-5-Precision-DSP-block-simulations/m-p/1710248

Hi, Thank you for looking into this further. I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared



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Re: Agilex 5 Precision DSP block simulations

Hi, Thank you for looking into this further. I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared

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      Hi, Thank you for looking into this further. I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared
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      Hi,   Thank you for looking into this further. I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared incorrect previously. Regarding the MAC; i still see an issue and there has now been an IPS case opened for it (via our AE). Since there is an IPS case...
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