Customized high performance low power processor for binaural speaker localization

One of the key problems for hearing impaired persons represents the cocktail party scenario, in which a bilateral conversation is surrounded by other speakers and noise sources. State-of-the-art beamforming techniques are able to segregate specific sound sources from the environment, presupposing the position of the speaker. The speaker position can be estimated in the frontal azimuth-plane with a probabilistic localization algorithm from the binaural microphone input of the both-eared hearing aid system. However, the binaural speaker localization requires computationally complex audio processing and filtering. The high computational complexity combined with low energy requirements to meet the battery constraints of hearing aid devices presents an implementation challenge. This paper proposes a customized C programmable processor design to implement the speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151x speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices. The algorithms supported by the previously proposed implementations are approximately 15x less computationally demanding.